1. Field of the Invention
The present invention relates in general to a process for fabrication of non-volatile memory cells. In particular, the present invention relates to a process for fabrication of non-volatile memory cells having improved voltage coupling ratio. More particularly, the present invention relates to a process for fabrication of non-volatile memory cells having improved voltage coupling ratio by utilizing liquid phase deposition to introduce polysilicon spacers onto the floating gates of non-volatile memory cells.
2. Technical Background
Conventional non-volatile semiconductor memory cells normally require high voltage for effecting writing and erasing operation to the memory cells. The writing and erasing voltages are considered high when compared to their normal read operation voltage, typically set at 3 to 5 volts. A typical write/erase voltage for EPROM devices is 12V, while for EEPROM it is about 18-22V. A high voltage coupling ratio is, in turn, needed to support such high operating voltage for writing and erasing operations.
Conventional non-volatile memory cell fabrication techniques incorporate photomasking as part of the fabrication process. However, precision alignment during the photomasking process is vital in the fabrication of present-day high capacity memory devices. Such precision alignment is considered relatively difficult to implement due to the finer resolution requirements in the fabrication of high density memory devices. Precision photomasking process steps, which add to the process time requirement, therefore represents increased cost for the fabrication of semiconductor devices. Thus, it is always desirable to reduce, or even avoid, the use of photomasking process steps during semiconductor fabrication procedures.
A typical prior art process for fabricating non-volatile memory cells is explained below with reference to the sets of FIGS. 1a-1d and 2a-2e together. FIGS. 1a-1d show the layout of the non-volatile memory cell, and FIGS. 2a-2e show the same non-volatile memory cell but with selected cross sections from related stages of the fabrication procedure. For example, active region 100 as seen in FIG. 1a is defined on a substrate for the memory device, designated as reference numeral 10 in FIG. 2a, in which FIG. 2a is the view of the cross section taken along the 2a--2a line in FIG. 1a.
Active region 100 is defined on substrate 10. An oxide layer with a thickness of about 300-500 .ANG. and a nitride layer of about 1,500-2,000 .ANG. are subsequently formed on substrate 10. A thermal oxidation procedure is then performed to form field oxide layer 30 in the area on substrate 10 excluding active region 100. The oxide and nitride layers are then removed, and channel oxide layer 20 is formed on active region 100 to obtain the structure shown in the cross-sectional view of FIG. 2a. For flash memories, the thickness of channel oxide layer 20 is about 100 .ANG., while for typical EPROMs, this thickness is about 200 .ANG..
Next, referring to FIGS. 1b and 2b concurrently, in which FIG. 2b is the cross section taken along the 2b--2b line in FIG. 1b, a first polycide layer with a thickness of about 1,500-2,000 .ANG. is then deposited, and a region for floating gate 40 is defined out of the first polycide layer as indicated by shaded-line area 40 shown in FIG. 1b, as well as indicated by shaded-line portion 40 in FIG. 2b. A relatively thinner layer of dielectric material 50 with a thickness of about 100-250 .ANG. is then formed thereon. The dielectric material can be a typical oxide/nitride/oxide structure.
Then, referring to FIGS. 1c and 2c, in which FIG. 2c is again the cross section taken along the 2c--2c line in FIG. 1c, a second polycide layer with a thickness of about 2,000 .ANG. is formed thereon and followed by the formation of an electrically conductive metal silicide layer with a thickness of about 1,500-2,000 .ANG.. A photomasking procedure is then implemented by first applying layer of photoresist 61 covering the second polycide and metal silicide layers. Exposure and subsequent processing applied to the layer of photoresist 61 define the contour for control gate 60 of the memory cell being fabricated. This results in the structural configuration as shown by dot-filled area 60 in the layout view of FIG. 1c, as well as being indicated by dot-filled area 60 of FIG. 2c.
Next, referring to FIGS. 1d and 2d, with the cross-sectional view of FIG. 2d taken along the 2d--2d line in FIG. 1d, an etching process is performed before the layer of photoresist is removed to etch away the portions of dielectric layer 50 and floating gate 40 not being covered by photoresist 61. After this etching, photoresist layer 61 is removed and obtain source region 70 and drain region 80 for the memory cell. This can be observed as seeing the floating gate layer being designated by shaded-line portion 41 in FIG. 1d. A view showing the cross section of the completed non-volatile memory cell as shown in FIG. 2d, with another cross-sectional view taken along the 2e--2e line in FIG. 1d, is shown in FIG. 2e to reveal the structural configuration of the non-volatile memory cell from another direction.
FIG. 3 is a schematic diagram of the equivalent circuit of a non-volatile memory cell showing the effect of equivalent capacitance established in the cell structural configuration, which includes a channel oxide 20, a floating gate 40, a dielectric layer 50, a control gate 60, a drain D, a source S and a base B. When a non-volatile memory cell is activated by applying appropriate voltages to the relevant terminals of the device, there will be capacitance C.sub.1 established between floating gate layer 40 and control gate layer 60 of the conventional non-volatile memory cell. A reference to the cross-sectional views FIGS. 2d and 2e, of the completed fabrication of a non-volatile memory cell, indicates that capacitance C.sub.1 is across dielectric layer 50. There is also another capacitance C.sub.2 established across channel oxide layer 20. If the voltage applied to control gate 60 is V.sub.1, while the voltage to floating gate 40 is V.sub.2, there exists a relationship between the voltages and capacitances as follows: EQU V.sub.1 =[C.sub.1 /(C.sub.1 +C.sub.2)]V.sub.2
Based on the characteristic of the above expression, a larger C.sub.1 implies a larger coupling ratio for the voltages. In other words, a larger C.sub.1 enables the reduction in the voltage required by the non-volatile memory cell for the data bit writing and erasing operation. The reduced writing/erasing voltage in turn enables the simplification of the peripheral circuitry for the memory cell that supports the writing/erasing operation of the memory device.